Delivery of high quality parts and controlling production costs are often competing objectives for semiconductor manufacturers as they are for other types of businesses. One area where these objectives compete is in the testing of wafers and integrated circuit packages.
Various test techniques include sequential chain testing or "scan" testing, and built-in self-testing (BIST). Testers that use scan and/or BIST techniques typically require moderate incremental hardware costs. However, the yield rate for circuits subjected to scan and BIST tests alone is not great enough to proceed from wafer test to package assembly because some circuits may pass the scan and BIST tests and still be inoperable when packaged. Therefore, machine-mode parallel pattern testing and parametric tests are performed after the scan and BIST tests. The drawback to machine-mode and parametric testing is that they require a full complement of tester channels for signals and power. The result is that duplication of expensive test equipment is required to increase test throughput using conventional parallel test technology with microprocessor and VLSI devices.
Conventional parallel testing of microprocessor circuits has been found to be expensive relative to the corresponding increase in testing throughput. As explained above, a large part of the expense is driven by the hardware requirements for machine-mode and parametric testing. In addition, relatively short test times may not justify the hardware expense.